An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. Each cell 100 contains a storage capacitor 140 and an access field effect transistor or transfer device 120. For each cell, one side of the storage capacitor 140 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 140 is connected to the drain of the transfer device 120. The gate of the transfer device 120 is connected to a signal known in the art as a word line 180. The source of the transfer device 120 is connected to a signal known in the art as a bit line 160 (also known in the art as a digit line). With the memory cell 100 components connected in this manner, it is apparent that the word line 180 controls access to the storage capacitor 140 by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line 160 to be written to or read from the storage capacitor 140. Thus, each cell 100 contains one bit of data (i.e., a logic “0” or logic “1”).
In FIG. 2 a DRAM circuit 240 is illustrated. The DRAM 240 contains a memory array 242, row and column decoders 244, 248 and a sense amplifier circuit 246. The memory array 242 consists of a plurality of memory cells 200 (constructed as illustrated in FIG. 1) whose word lines 280 and bit lines 260 are commonly arranged into rows and columns, respectively. The bit lines 260 of the memory array 242 are connected to the sense amplifier circuit 246, while its word lines 280 are connected to the row decoder 244. Address and control signals are input on address/control lines 261 into the DRAM 240 and connected to the column decoder 248, sense amplifier circuit 246 and row decoder 244 and are used to gain read and write access, among other things, to the memory array 242.
The column decoder 248 is connected to the sense amplifier circuit 246 via control and column select signals on column select lines 262. The sense amplifier circuit 246 receives input data destined for the memory array 242 and outputs data read from the memory array 242 over input/output (I/O) data lines 263. Data is read from the cells of the memory array 242 by activating a word line 280 (via the row decoder 244), which couples all of the memory cells corresponding to that word line to respective bit lines 260, which define the columns of the array. One or more bit lines 260 are also activated. When a particular word line 280 and bit lines 260 are activated, the sense amplifier circuit 246 connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line 260 by measuring the potential difference between the activated bit line 260 and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
The memory cells of dynamic random access memories (DRAMs) are comprised of two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density. As component density has increased, cell capacitance has had to be decreased because of the need to maintain isolation between adjacent devices in the memory array. However, reduction in memory cell capacitance reduces the electrical signal output from the memory cells, making detection of the memory cell output signal more difficult. Thus, as the density of DRAM devices increases, it becomes more and more difficult to obtain reasonable storage capacity.
The majority of DRAM's currently use either stacked capacitor or trench capacitor cells. (See generally, J. Rabaey, Digital Integrated Circuits, Prentice Hall, 585–590 (1996); W. P. Noble et al., “The Evolution of IBM CMOS DRAM Technology,” IBM J. Research and Development, 39-1/2, 167–188 (1995)). Three transistor, 3-T, planar gain cells, originally used in DRAM's, were abandoned as higher densities were required. This is because three transistor planar gain cells generally require a minimum cell area of twenty-four square photolithographic features (24F2) and can in some case require an area as large as forty-eight square photolithographic features (48F2).
Some “embedded” DRAM memories currently use 3-T gain cells. (See generally, M. Mukai et al., “Proposal of a Logic Compatible Merged-Type Gain Cell for High Density Embedded.,” IEEE Trans. on Electron Devices, 46-6, 1201–1206 (1999)). These “embedded” 3-T gain cells are more compatible with a standard CMOS logic process than DRAM memory cells which use either stacked capacitors or trench capacitors. That is, stacked capacitors require special processes not available in a CMOS logic process. Trench capacitors are possible in a CMOS logic process, but three additional masking steps are required. (See generally, H. Takato et al., “Process Integration Trends for Embedded DRAM,” Proceedings of ULSI Process Integration, Electrochemical Society Proceedings, 99-18, 107–19 (1999)). As a result 3-T DRAM gain cells are the easiest technique to use to incorporate embedded memory into microprocessors. These 3-T gain cells however are planar and they use conventional planar CMOS devices which again requires a cell area which is large. For reference, DRAM cell areas for either stacked capacitor or trench capacitor cells are typically 6F2 or 8F2.
It is becoming more and more difficult to fabricate stacked capacitor cells with the required DRAM cell capacitance of around 30 fF. Very high aspect ratio capacitors are required with height to diameter ratios of the order ten and consideration is being given to employing high-K dielectrics. Various gain cells have been proposed from time to time. (See generally, L. Forbes, “Single Transistor Vertical Memory (DRAM) Gain Cell,” U.S. application Ser. No. 10/231,397; L. Forbes, “Merged MOS-Bipolar-Capacitor Memory (DRAM) Gain Cell,” U.S. application Ser. No. 10/230,929; L. Forbes, “Vertical Gain Cell,” U.S. application Ser. No. 10/379,478; L. Forbes, “Embedded DRAM Gain Memory Cell,” U.S. application Ser. No. 10/309,873; T. Ohsawa et al., “Memory Design Using One Transistor Gain Cell on SOI,” IEEE Int. Solid State Circuits Conference, San Francisco, 152–153 (2002); S. Okhonin, M. Nagoga, J. M. Sallese, P. Fazan, “A SOI Capacitor-less IT-DRAM Cell,” Late News 2001 IEEE Intl. SOI Conference, Durango, Colo., 153–154; L. Forbes, “Merged Transistor Gain Cell for Low Voltage DRAM (Dynamic Random Access) Memories,” U.S. Pat. No. 5,732,014, 24 Mar. 1998, continuation granted as U.S. Pat. No. 5,897,351, 27 Apr. 1999; Sunouchi et al., “A Self-Amplifying (SEA) Cell for Future High Density DRAMs,” Ext. Abstracts of IEEE Int. Electron Device Meeting, 465–468 (1991); M. Terauchi et al., “A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMS,” VLSI Tech. Symposium, 21–22 (1993); S. Shukuri et al., “Super-Low-Voltage Operation of a Semi-Static Complementary Gain RAM Memory Cell,” VLSI Tech. Symposium, 23–24 (1993); S. Shukuri et al., “Super-Low-Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell,” Ext. Abs. of IEEE Int. Electron Device Meeting, 1006–1009 (1992); S. Shukuri et al., “A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAM's,” IEEE Trans. on Electron Devices, 41, 926–931 (1994); H. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” IEEE Int. Electron Devices Meeting, 635–638 (1993); W. Kim et al., “An Experimental High-Density DRAM Cell with a Built-in Gain Stage,” IEEE J. of Solid-State Circuits, 29, 978–981 (1994); W. H. Krautschneider et al., “Planar Gain Cell for Low Voltage Operation and Gigabit Memories,” Proc. VLSI Technology Symposium, 139–140 (1995); D. M. Kenney, “Charge Amplifying Trench Memory Cell,” U.S. Pat. No. 4,970,689, 13 Nov. 1990; M. Itoh, “Semiconductor Memory Element and Method of Fabricating the Same,” U.S. Pat. No. 5,220,530, 15 Jun. 1993; W. H. Krautschneider et al., “Process for the Manufacture of a High Density Cell Array of Gain Memory Cells,” U.S. Pat. No. 5,308,783, 3 May 1994; C. Hu et al., “Capacitorless DRAM Device on Silicon on Insulator Substrate,” U.S. Pat. No. 5,448,513, 5 Sep. 1995; S. K. Banerjee, “Method of Making a Trench DRAM Cell with Dynamic Gain,” U.S. Pat. No. 5,066,607, 19 Nov. 1991; S. K. Banerjee, “Trench DRAM Cell with Dynamic Gain,” U.S. Pat. No. 4,999,811, 12 Mar. 1991; Lim et al., “Two Transistor DRAM Cell,” U.S. Pat. No. 5,122,986, 16 Jun. 1992; Blalock et al., “An Experimental 2T Cell RAM with 7 ns Access at Low Temperature,” Proc. VLSI Technology Symposium, 13–14 (1990)).
What is required is a small area gain cell, typically 6F2 or 8F2, which has the same cell area and density as current DRAM's but one which does not require the high stacked capacitor or deep trench capacitor.